The present application relates to a delta-sigma modulator, an arrangement with two delta-sigma modulators and to a method for signal conversion.
A delta-sigma modulator typically comprises a loop-filter, a quantizer and a feedback digital-to-analog converter. A single-bit delta-sigma modulator is popular primarily because of the inherent linearity of a single-bit feedback digital-to-analog converter. On the other hand, a single-bit quantizer makes the delta-sigma modulator a strongly non-linear system. The single-bit delta-sigma modulator consequently produces very large tones near the half of a sampling frequency, also referred to as idle tones, as a result of limit cycles. The idle tones are particularly relevant, if another signal near the half of the sampling frequency interferes with a bit stream of the delta-sigma modulator. In this case, a tone gets folded down, for example, in the baseband.
Document US 2013/0135131 A1 refers to an idle tone suppression circuit comprising a sigma-delta analog-to-digital converter.
Publication Y. Matsuya et al, “A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping”, IEEE Journal of Solid-State Circuits, Vol. SC-22, pp. 921-929, 1987, describes a monolithic audio analog-to-digital converter.